FIG. 1 shows a conventional Field Programmable Gate Array (FPGA) 1 having an array of configurable logic blocks (CLBs) 2 surrounded by input/output blocks (IOBs) 3. The CLBs 2 are individually programmable and can be configured to perform a variety of logic functions ranging from simple AND gates to more complex functions of a few input signals. A programmable interconnect structure 4 includes a matrix of programmable switches (PSMs) 5 which can be programmed to selectively route signals between the various CLBs 2 and IOBs 3 and thus produce more complex functions of many input signals. The IOBs 3 can be configured to drive output signals from the CLBs 2 to external pins (not shown) of FPGA 1 and/or to receive input signals from the external FPGA pins.
The CLBs 2, IOBs 3, and PSMs 5 of FPGA 1 are programmed by loading configuration data into memory cells (not shown for simplicity) connected to CLBs 2, IOBs 3, and PSMs 5. These memory cells control various switches and multiplexers within respective CLBs 2, IOBs 3, and PSMs 5 which implement logic and routing functions specified by the configuration data in the memory cells. Configuration data is provided to FPGA 1 via a configuration port 6 and thereafter routed to the memory cells using a dedicated configuration structure (not shown here but described in U.S. Pat. Nos. Re. 34,363, 5,430,687, 5,742,531, and 5,844,829). Configuration port 6 is connected to the dedicated configuration structure by a configuration access port (CAP) 7, which is essentially a bus access point. Further information regarding various types of FPGAs can be found in "The Programmable Logic Data Book 1998", published in 1998 by Xilinx, Inc., and available from Xilinx, Inc., 2100 Logic Drive, San Jose, Calif. 95124.
Configuration data is typically downloaded to an FPGA from a host system such as a personal computer or workstation using an FPGA interface cable, as illustrated in FIG. 2. Well known design tool software operating on a suitable microprocessor within host system 20 creates a configuration bitstream which embodies the logic functions desired to be implemented by the target FPGA. The configuration bitstream is downloaded from host system 20 to interface cable 15 using, for instance, a serial port or a USB port. The interface cable 15 preferably includes an on-board FPGA that customizes the configuration bitstream received from the host system 20 into a format usable by target FPGA 10, although in some embodiments host system 20's microprocessor is used to customize the configuration bitstream for target FPGA 10. Since an FPGA is able to customize configuration data at a rate much faster than that of a microprocessor, FPGA interface cables having an on-board FPGA provide superior performance.
Interface cables having an on-board FPGA typically include an associated non-volatile memory for storing the on-board FPGA's default configuration design. When the interface cable is powered up, the on-board FPGA reads its default configuration design from the associated memory, and then configures itself accordingly. Should it become desirable to change or update the configuration of the on-board FPGA, e.g., so as to enable the interface cable to be used with target devices of varying configurations and compatibility standards, the associated memory is re-programmed with the new configuration design. The interface device is then reset. Upon subsequent boot-up of the interface cable, the on-board FPGA reads the new configuration design from the associated memory, and then configures itself accordingly.
Reconfiguring the on-board FPGA by using a different non-volatile memory requires actually removing an IC device from the board and replacing it. This is typically not possible for an end user. Further, resetting the interface cable typically requires the user to manually activate a reset switch on the interface device, which is inconvenient and time consuming. Further, since the entire interface cable is reset in order to reconfigure the on-board FPGA, the microcontroller must also be reset and then booted up again, which undesirably consumes additional time. In addition, since the new configuration design is typically written to the same memory space which stores the default configuration design, the default configuration design is no longer available after reconfiguration of the on-board FPGA. Thus, if a problem develops with the new configuration design, the default configuration design must be re-programmed into the memory, and the interface cable again reset.